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giuseppe airof
This course is part of the Master Degree in Computer Engineering, focused on Embedded Systems, given during the II teaching period of the II year. The course aims at describing the concept of reliability, presenting the main fault tolerant design technique, as well as the techniques for reliability evaluation. The course will deepen the different redundancy techniques such as hardware redundancy, time redundancy and information redundancy, and it will present some case study taken from real applications.
TU Delft
With the continuous scaling of transistor feature sizes, the VLSI chip density is exponentially increasing. This results in a significant complexity of today's and future VLSI technology; such a complexity has reached the point where billions of transistors are integrated on a single chip (as it is the case for System on Chip). To guarantee customer's satisfaction, produced VLSI chips have to be reliable and fully tested. Verification and production testing represent 50 to 60% of the chips production total cost, and are now the biggest cost of the technology. It has been known for a while that tackling problems associated with testing VLSI chips at earlier design stage levels significantly reduces the testing cost. Thus it is important for hardware designers to be exposed to concepts of VLSI testing which can help them design better products at lower cost.
Tallinn University of Technology
Dependability related system design criteria: testability, diagnosability, reliability, fault-tolerance, safety, security, dependability. Economic tradeoffs of testability and quality policy. Measures for controllability, observability, testability, diagnosability. Design for testability: ad hoc and structural methods. Scan-Path design. Linear feedback shift registers. Pseudorandom testing and signature analysis. Self-testing systems, circular self-testing, store-and-generate universal test architectures. Test standards: Boundary Scan, IEEE P1500 standard for System on Chip (SoC) test. Tesating of Networks-on-Chip (NoC). Embedded self-diagnosis. Optimization of self-testing and self-diagnosis. On-line testing. Self-repair in systems. Error detecting and correcting codes. Evaluation of dependability.
University of Montpellier
This course deals with test and testability of integrated circuits. It introduces the concepts, methods and tools that can guarantee integrated circuit testability. A test sequence, in the frame of industrial testing, should be able to verify the datasheet specifications of a logic circuit through a dedicated test program executed by an advanced industrial tester (Advantest V93K). It allows us to understand how the characterization phase leads to the AC/DC performances specified in the datasheet and how the obtained specification is guarantied by the production test.
University of Montpellier
This course deals with test and testability of integrated circuits. It introduces the concepts, methods and tools that can guarantee integrated circuit testability. A test sequence, in the frame of industrial testing, should be able to verify the datasheet specifications of a logic circuit through a dedicated test program executed by an advanced industrial tester (Advantest V93K). It allows us to understand how the characterization phase leads to the AC/DC performances specified in the datasheet and how the obtained specification is guarantied by the production test.